The code is synthesisable, and the cell usage statistics for Virtex-5 FPGA is shown below: Variable bint : std_logic_vector ( 7 downto 0 ) := bin įor i in 0 to 7 loop - repeating 8 times.īcd ( 11 downto 1 ) := bcd ( 10 downto 0 ) -shifting the bits.īint ( 7 downto 1 ) := bint ( 6 downto 0 ) Variable bcd : std_logic_vector ( 11 downto 0 ) := ( others => ' 0' )
Function to_bcd ( bin : std_logic_vector ( 7 downto 0 ) ) return std_logic_vector is
